In recent years, the development of a variety of electronic equipment in accordance with high-speed digital interface standards, such as the HDMI (High Definition Multimedia Interface) standard or DVI (Digital Visual Interface) standard, is in progress (DDWG, “Digital Visual Interface,” Revision 1.0, Apr. 2, 1999, Internet <URL:http://www.ddwg.org/>). The HDMI standard, in particular, defines the transmission of an audio signal and control signal during the video blanking intervals. These high-speed digital interface standards adopt the so-called TMDS (Transmission Minimized Differential Signaling) serial transmission system.
FIG. 6 is a block diagram showing an example of a conventional high-speed digital interface decode receiver. Referring to FIG. 6, the conventional high-speed digital will be described.
In FIG. 6, the high-speed digital interface decode receiver (hereafter abbreviated to the interface decode receiver) includes a plurality of differential buffers 60a, 60b, 60c, 60d, a TMDS decoder circuit 61, a multiplier circuit 62, and a video/audio processing circuit 65. The interface decode receiver is composed of a receiver LSI (Large Scale Integrated Circuit) 66.
The interface decode receiver receives digital signals in accordance with a high-digital interface standard.
A clock-channel signal B of the digital signals is applied to the multiplier circuit 62 as a clock signal D via the differential buffer 60d. The multiplier circuit 62 multiplies the clock signal D, and outputs the multiplied signal D as a multiplied clock signal E.
Signals A of the digital signals except the clock channel are applied to the TMDS decoder 61 via the differential buffers 60a, 60b, 60c. The TMDS decoder 61 serial/parallel converts and decodes the signals except the clock channel for output of a synchronization signal G and a video/audio signal F.
The video/audio processing circuit 65 separates the video/audio signal F output from the TMDS decoder 61 into a video signal I, audio signal J, and control signal K for output.
In the conventional interface decode receiver, the digital signals in accordance with the high-speed digital interface standard are decoded by means of the foregoing operation.
However, in cases where the conventional interface decode receiver receives digital signals in formats that cannot be decoded, the receiver LSI 66 may operate at speeds beyond a specified speed. This may cause abnormalities such as thermal runaway, increases in consumption power, or circuit destruction.